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december 2006 rev 6 1/24 1 m48z512a m48z512ay, m48z512av 4 mbit (512 kbit x 8) zeropower? sram features integrated, ultra low power sram, power-fail control circuit, and battery conventional sram operation; unlimited write cycles 10 years of data retention in the absence of power automatic power-fail chip deselect and write protection two write protect voltages: (v pfd = power-fail deselect voltage) ?m48z512a: v cc = 4.75 to 5.5v, 4.5v v pfd 4.75v ?m48z512ay: v cc = 4.5 to 5.5v, 4.2v v pfd 4.5v ?m48z512av: v cc = 3.0 to 3.6v, 2.8v v pfd 3.0v battery internally isolat ed until power is applied pin and function compatible with jedec standard 512k x 8 srams soic package provides direct connection for a snaphat top which contains the battery snaphat housing (battery) is replaceable equivalent surface-mount (smt) solution requires a 28-pin m40z300/w and a stand- alone 128k x8 lpsram (snaphat ? top to be ordered separately pmdip32 is an ecopack package description the m48z512a/y/v zeropower ? ram is a non-volatile, 4,194,304-bit static ram organized as 524,288 words by 8 bits. the devices combine an internal lithium battery, a cmos sram and a control circuit in a plastic, 32-pin dip module. for surface-mount environments st provides an equivalent smt solution consisting of a 28-pin, 330mil soic nvram supervisor (m40z300/w) and a 32-pin, (type ii tsop, 10 x 20mm) 4mb lpsram. both 5v and 3v versions are available (see table 2 on page 7 ). the unique design allows the snaphat ? battery package to be mounted on top of the soic package after the completion of the surface- mount process. insertion of the snaphat housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. the snaphat housing is keyed to prevent reverse insertion. the snaphat battery package is shipped separately in plastic anti-static tubes or in tape & reel form. the part number is ?m4z32-br00sh1. pmdip32 (pm) module 32 1 www.st.com
contents m48z512a m48z512ay m48z512av 2/24 contents 1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 v cc noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
m48z512a m48z512ay m48z512av list of tables 3/24 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. equivalent surface-mount (smt) solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 11. power down/up trip points dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 12. pmdip32 ? 32-pin plastic dip module, package mechanical data . . . . . . . . . . . . . . . . . . 18 table 13. soh28 ? 28-lead plastic small outline, battery snaphat, package mechanical data . . 19 table 14. sh ? 4-pin snaphat housing for 48mah battery, package mechanical data . . . . . . . . . . 20 table 15. sh - 4-pin snaphat housing for 120mah battery, package mechanical data . . . . . . . . . 21 table 16. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 17. snaphat battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 18. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
list of figures m48z512a m48z512ay m48z512av 4/24 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. dip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. hardware hookup for equivalent surface-mount (smt) solution . . . . . . . . . . . . . . . . . . . . . 7 figure 5. chip enable or output enable controlled, read mode ac waveforms . . . . . . . . . . . . . . . . 9 figure 6. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. write enable controlled, write ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. pmdip32 ? 32-pin plastic dip module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13. soh28 ? 28-lead plastic small outline, battery snaphat, package outline . . . . . . . . . . 19 figure 14. sh ? 4-pin snaphat housing for 48mah battery, package outline. . . . . . . . . . . . . . . . . . 20 figure 15. sh ? 4-pin snaphat housing for 120mah battery, package outline. . . . . . . . . . . . . . . . . 21
m48z512a m48z512ay m48z512av device overview 5/24 1 device overview figure 1. logic diagram table 1. signal names a0-a18 address inputs dq0-dq7 data inputs/outputs e chip enable input g output enable input w write enable input v cc supply voltage v ss ground ai02043 19 a0-a18 w dq0-dq7 v cc m48z512a m48z512ay m48z512av g v ss 8 e
device overview m48z512a m48z512ay m48z512av 6/24 figure 2. dip connections figure 3. block diagram a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a15 a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a16 a18 v cc ai02044 m48z512a m48z512ay m48z512av 10 1 2 5 6 7 8 9 11 12 13 14 15 16 30 29 26 25 24 23 22 21 20 19 18 17 a12 a14 w a17 3 4 28 27 32 31 ai02045 internal battery e v cc v ss voltage sense and switching circuitry 512k x 8 sram array a0-a18 dq0-dq7 w g power e
m48z512a m48z512ay m48z512av device overview 7/24 figure 4. hardware hookup for equivalent surface-mount (smt) solution 1. for pin connections, see individual da tasheet for m48z300/300w at www.st.com. 2. connect ths pin to v out if 4.2v v pfd 4.5v (m48z512ay) or connect ths pin to v ss if 4.5v v pfd 4.75v (m48z512a). 3. connect ths pin to v ss if 2.8v v pfd 3.0v (m48z512av). 4. snaphat ? top ordered separately. table 2. equivalent surface-mount (smt) solution nvram lpsram supervisor ths pin (1) 1. connection of threshold select pi n (pin 13) of supervisor (m40z300/300w). m48z512a 5v 4mb lpsram m40z300 v ss m48z512ay 5v 4mb lpsram m40z300 v out m48z512av 3v 4mb lpsram m40z300w v ss ai03631 e1 con v ss v out ths (2)(3) a m40z300/w e b e2 con e3 con e4 con v ss v cc 4mb lpsram e a0-a18 w dq0-dq7 snaphat battery (4) rst bl
operating modes m48z512a m48z512ay m48z512av 8/24 2 operating modes the m48z512a/y/v also has its own power-fail detect circuit. the control circuitry constantly monitors the single v cc supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system operation brought on by low v cc . as v cc falls below the switchover voltage (v so ), the control circuitry connects the battery which maintains data until valid power returns. the zeropower ? ram replaces industry standard sram s. it provides the nonvolatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. 2.1 read mode the m48z512a/y/v is in the read mode whenever w (write enable) is high and e (chip enable) is low. the device architecture allows ripple-through access of data from eight of 4,194,304 locations in the static storage array. thus, the unique address specified by the 19 address inputs defines which one of the 524,288 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e (chip enable) and g (output enable) access times are also satisfied. if the e and g access times are not met, valid data will be available after the later of chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address inputs are changed while e and g remain low, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. table 3. operating modes (1) 1. see table 11 on page 17 for details. mode v cc e g w dq0-dq7 power deselect 4.75 to 5.5v or 4.5 to 5.5v or 3.0 to 3.6v v ih x x high z standby write v il xv il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (2) 2. x = v ih or v il ; v so = battery back-up switchover voltage. x x x high z cmos standby deselect v so (2) x x x high z battery back-up mode
m48z512a m48z512ay m48z512av operating modes 9/24 figure 5. chip enable or output enable controlled, read mode ac waveforms 1. write enable (w ) = high. figure 6. address controlled, read mode ac waveforms 1. chip enable (e ) and output enable (g ) = low, write enable (w ) = high. ai01221 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz data out a0-a18 e g dq0-dq7 valid ai01220 taxqx data valid a0-a18 dq0-dq7 tavav tavqv
operating modes m48z512a m48z512ay m48z512av 10/24 2.2 write mode the m48z512a/y/v is in the write mode whenever w and e are active. the start of a write is referenced from the latter occu rring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for a minimum of t ehax from e or t whax from w prior to the initiation of another read or write cycle. data-in must be valid t dveh or t dvwh prior to the end of write and remain valid for t ehdx or t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g , a low on w will disable the outputs t wlqz after w falls. table 4. read mode ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70c or -40 to 85c; v cc = 4.75 to 5.5v, 4.5 to 5.5v, or 3.0 to 3.6v (except where noted). m48z512a/y -70 m48z512a/y/v -85 unit min max min max t avav read cycle time 70 85 ns t avqv address valid to output valid 70 85 ns t elqv chip enable low to output valid 70 85 ns t glqv output enable low to output valid 35 45 ns t elqx (2) 2. c l = 5pf. chip enable low to output transition 5 5 ns t glqx (2) output enable low to output transition 5 5 ns t ehqz (2) chip enable high to output hi-z 30 35 ns t ghqz (2) output enable high to output hi-z 20 25 ns t axqx address transition to output transition 5 5 ns
m48z512a m48z512ay m48z512av operating modes 11/24 figure 7. write enable controlled, write ac waveforms 1. output enable (g ) = high. figure 8. chip enable controlled, write ac waveforms 1. output enable (g ) = high. ai01222 tavav twhax tdvwh data input a0-a18 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai01223 tavav tehax tdveh a0-a18 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
operating modes m48z512a m48z512ay m48z512av 12/24 2.3 data retention mode with valid v cc applied, the m48z512a/y/v operates as a conventional bytewide? static ram. should the supply volt age decay, the ram will automat ically power-fail deselect, write protecting itself t wp after v cc falls below v pfd . all outputs become high impedance, and all inputs are treated as ?don't care.? if power fail detection occurs during a valid access, the memory cycle continues to completion. if the memory cycle fails to terminate within the time t wp , write protection takes place. when v cc drops below v so , the control circuit switches power to the internal energy source which preserves data. the internal coin cell will mainta in data in the m48z512a/y/v af ter the initial application of v cc for an accumulated period of at least 10 years when v cc is less than v so . as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues for t er after v cc reaches v pfd to allow for processor stabilization. after t er , normal ram operation can resume. for more information on battery storage life refer to the application note an1012. table 5. write mode ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70c or -40 to 85c; v cc = 4.75 to 5.5v, 4.5 to 5.5v or 3.0 to 3.6v (except where noted). m48z512a/y ?70 m48z512a/y/v ?85 unit min max min max t avav write cycle time 70 85 ns t avwl address valid to write enable low 0 0 ns t avel address valid to chip enable low 0 0 ns t wlwh write enable pulse width 55 65 ns t eleh chip enable low to chip enable high 55 75 ns t whax write enable high to address transition 5 5 ns t ehax chip enable high to address transition 15 15 ns t dvwh input valid to write enable high 30 35 ns t dveh input valid to chip enable high 30 35 ns t whdx write enable high to input transition 0 0 ns t ehdx chip enable high to input transition 10 10 ns t wlqz (2)(3) 2. c l = 5pf. 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. write enable low to output hi-z 25 30 ns t avwh address valid to write enable high 65 75 ns t aveh address valid to chip enable high 65 75 ns t whqx (2)(3) write enable high to output transition 5 5 ns
m48z512a m48z512ay m48z512av operating modes 13/24 2.4 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store energy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low goin g spikes are generated or energy will be absorbed when overshoots occur. a ceramic bypass capacitor value of 0.1f (see figure 9 ) is recommended in order to provide the needed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate negative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, st recommends connecting a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). (schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface-mount). figure 9. supply voltage protection ai01223 tavav tehax tdveh a0-a18 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
maximum rating m48z512a m48z512ay m48z512av 14/24 3 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. caution: negative undershoots below ?0.3v are not allowed on any pin while in the battery back-up mode. do not wave solder soic to avoid damaging snaphat sockets. table 6. absolute maximum ratings symbol parameter value unit t a ambient operating temperature grade 1 0 to 70 c grade 6 -40 to 85 t stg storage temperature (v cc off) ?40 to 85 c t bias temperature under bias grade 1 0 to 70 c grade 6 ?40 to 70 t sld (1)(2) 1. for dip package: soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 sec onds). no preheating above 150c, or di rect exposure to ir reflow (or ir preheat) allowed, to avoid damaging the lithium battery. 2. for so package, lead-free (pb-free) lead finish: reflow at peak tem perature of 260c (total thermal budget not to exceed 245c for greater than 30 seconds). lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to 7 v v cc supply voltage m48z512a/512ay ?0.3 to 7.0 v m48z512av ?0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
m48z512a m48z512ay m48z512av dc and ac parameters 15/24 4 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. figure 10. ac measurement load circuit 1. excluding open drain output pins; 50pf for m48z512av. table 7. operating and ac measurement conditions (1) 1. output hi-z is defined as the point where data is no longer driven. parameter m48z512a/512ay m48z512av unit supply voltage (v cc ) 4.75 to 5.5v or 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature (t a ) grade 1 0 to 70 0 to 70 c grade 6 -40 to 85 -40 to 85 load capacitance (c l ) 100 50 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v table 8. capacitance symbol parameter (1)(2) 1. effective capacitance meas ured with power supply at 5v (m48z 512a/y) or 3.3v (m48z512av); sampled only, not 100% tested. 2. outputs deselected. min max unit c in input capacitance 10 pf c io (3) 3. at 25c. input/output capacitance 10 pf ai03903 c l = 100pf or 30 pf c l includes jig capacitance 650 ? device under test 1.75v
dc and ac parameters m48z512a m48z512ay m48z512av 16/24 figure 11. power down/up mode ac waveforms table 9. dc characteristics sym parameter test condition (1) 1. valid for ambient operating temperature: t a = 0 to 70c or -40 to 85c; v cc = 4.75 to 5.5v, 4.5 to 5.5v, or 3.0 to 3.6v (except where noted). m48z512a/y ?70 m48z512av ?85 unit min max min max i li (2) 2. outputs deselected. input leakage current 0v v in v cc 1 1 a i lo (2) output leakage current 0v v out v cc 1 1 a i cc supply current e = v il outputs open 115 50 ma i cc1 supply current (standby) ttl e = v ih 10 4 ma i cc2 supply current (standby) cmos e v cc ? 0.2v 5 3 ma v il input low voltage ?0.3 0.8 ?0.3 0.6 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 0.4 v v oh output high voltage i oh = ?1ma 2.4 2.2 v ai02385 v cc inputs outputs don't care high-z twp tfb tr trb valid valid recognized recognized v pfd (max) v pfd (min) v so ter tf tdr (including e) v ss
m48z512a m48z512ay m48z512av dc and ac parameters 17/24 table 10. power down/up ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70c or -40 to 85c; v cc = 4.75 to 5.5v, 4.5 to 5.5v, or 3.0 to 3.6v (except where noted). min max unit t f (2) 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/wr ite protection not occurring until 200s after v cc passes v pfd (min). v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. v pfd (min) to v ss v cc fall time m48z512a/y 10 s m48z512av 150 t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1 s t wpt write protect time m48z512a/y 40 150 s m48z512av 40 250 t er e recovery time 40 120 ms table 11. power down/up trip points dc characteristics symbol parameter (1)(2) 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70c or -40 to 85c; v cc = 4.75 to 5.5v, 4.5 to 5.5v, or 3.0 to 3.6v (except where noted). min typ max unit v pfd power-fail deselect voltage m48z512a 4.5 4.6 4.75 v m48z512ay 4.2 4.3 4.5 v m48z512av 2.8 2.9 3.0 v v so battery back-up switchover voltage m48z512a/y 3.0 v m48z512av 2.5 v t dr (3) 3. at 25c; v cc = 0v. expected data retention time 10 years
package mechanical information m48z512a m48z512ay m48z512av 18/24 5 package mechanical information figure 12. pmdip32 ? 32-pin plastic dip module, package outline 1. drawing is not to scale. table 12. pmdip32 ? 32-pin plastic dip module, package mechanical data symb mm inches typ min max typ min max a 9.27 9.52 0.365 0.375 a1 0.38 0.015 b 0.43 0.59 0.017 0.023 c 0.20 0.33 0.008 0.013 d 42.42 43.18 1.670 1.700 e 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e3 38.10 1.50 ea 14.99 16.00 0.590 0.630 l 3.05 3.81 0.120 0.150 s 1.91 2.79 0.075 0.110 n32 32 pmdip a1 a l b e1 d e n 1 ea e3 s c
m48z512a m48z512ay m48z512av package mechanical information 19/24 figure 13. soh28 ? 28-lead plastic small outline, battery snaphat, package outline 1. drawing is not to scale. table 13. soh28 ? 28-lead plastic small outline, battery snaphat, package mechanical data symbol mm inch typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.30 0.006 0.012 d 17.70 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e1.27? ?0.050? ? eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 0 8 0 8 n28 28 cp 0.10 0.004 soh-a e n d c l a1 1 h a cp be a2 eb
package mechanical information m48z512a m48z512ay m48z512av 20/24 figure 14. sh ? 4-pin snaphat housing for 48mah battery, package outline 1. drawing is not to scale. table 14. sh ? 4-pin snaphat housing for 48mah battery, package mechanical data symb mm inches typ min max typ min max a9.780.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shzp-a a1 a d e ea eb a2 b l a3
m48z512a m48z512ay m48z512av package mechanical information 21/24 figure 15. sh ? 4-pin snaphat housing for 120mah battery, package outline 1. drawing is not to scale. table 15. sh - 4-pin snaphat housing for 120mah battery, package mechanical data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 0.335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 0.710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shzp-a a1 a d e ea eb a2 b l a3
part numbering m48z512a m48z512ay m48z512av 22/24 6 part numbering caution: do not place the snaphat batt ery package ?m4zxx-br00sh? in conductive foam as it will drain the lithium button-cell battery. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. table 16. ordering information scheme example: m48z 512ay ?70 pm 1 device type m48z supply voltage and write protect voltage 512a = v cc = 4.75 to 5.5v; v pfd = 4.5 to 4.75v 512ay = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v 512av = v cc = 3.0 to 3.6v; v pfd = 2.8 to 3.0v speed ?70 = 70ns (for m48z512a/y) ?85 = 85ns (for m48z512a/y/v) package (1) 1. the soic package (soh28) requi res the battery package (snaphat ? ) which is ordered separately under the part number ?m4zxx-br00sh? in plastic tube or ?m4zxx-br00shtr? in tape & reel form. pm = pmdip32 temperature range 1 = 0 to 70c 6 = -40 to 85c table 17. snaphat battery table part number description package m4z28-br00sh lithium battery (48mah) snaphat sh m4z32-br00sh lithium battery (120mah) snaphat sh
m48z512a m48z512ay m48z512av revision history 23/24 7 revision history table 18. revision history date version revision details march 2000 1.0 first issue 19-jul-00 1.1 m48z12av added 15-jan-01 1.2 changed lpsram device ( ta b l e 2 ) 19-dec-01 2.0 reformatted; added temperature information ( ta b l e 4 , ta b l e 5 , ta b l e 8 , ta b l e 9 , ta b l e 1 0 , and ta bl e 1 1 ); remove chipset option from ordering information ( ta b l e 1 6 ); remove reference to ?clock? 08-feb-02 2.1 remove 85ns speed grade ( ta b l e 4 , ta b l e 5 , and ta b l e 9 ) 29-may-02 2.2 modify reflow time and temperature footnotes ( ta b l e 6 ) 18-nov-02 2.3 modified smt text ( figure 1 , figure 4 , and ta b l e 2 ) 17-sep-03 2.4 remove references to m68xxx (obsolete) part ( figure 4 and ta b l e 2 ); update disclaimer 30-nov-04 3.0 reformatted; remove extended temperature references ( ta bl e 1 6 ) 21-dec-04 4.0 update marketing status for q ualification, correct drawing ( figure 4 and ta b l e 1 6 ) 22-feb-05 5.0 ir reflow, so package updates ( ta b l e 6 ) 21-dec-2006 6 document reformatted. ecopack package text added on coverpage. note 2 concerning leaded soic package removed below ta b l e 6 . updated pmdip32 package mechanical data in section 5: package mechanical information ; updated t a to include grade 1 (0 to 70c) and grade 6 (-40 to 85c).
m48z512a m48z512ay m48z512av 24/24 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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